← Back to areas
TN - EMCC Chesterfield Area WestCAD
Debug mode
Berths
| Berth |
Descr |
| 4749 |
|
| 4750 |
|
| 4751 |
|
| 4752 |
|
| 4753 |
|
| 4754 |
|
| 4756 |
|
| 4757 |
|
| 4762 |
|
| 4764 |
|
| 4767 |
|
| 4769 |
|
| 4773 |
|
| 4774 |
2Q33
|
| 4775 |
|
| 4776 |
|
| 4782 |
|
| 4783 |
|
| 4784 |
|
| 4790 |
|
| 4791 |
|
| 4792 |
|
| 4793 |
|
| 4794 |
|
| 4798 |
|
| 4833 |
|
| 4836 |
|
| 4837 |
1F50
|
| 4841 |
|
| 4842 |
|
| 4844 |
|
| 4845 |
|
| 4846 |
1V62
|
| 4847 |
|
| 4855 |
|
| 4856 |
|
| 4857 |
|
| 4858 |
|
| 4859 |
|
| 4864 |
|
| 4868 |
|
| 4869 |
|
| 4871 |
|
| 4877 |
|
| 4878 |
1V91
|
| 4879 |
|
| 4880 |
|
| 4887 |
|
| 4888 |
|
| 4889 |
|
| 4890 |
|
| 4891 |
|
| 4894 |
|
| 4895 |
|
| 4896 |
|
| 4897 |
|
| 4898 |
|
| 4899 |
|
| 4900 |
|
| 4901 |
|
| 4902 |
|
| COUT |
1F50
|
| DATE |
0710
|
| STIN |
|
| TRT1 |
FAIL
|
| TRT2 |
FAIL
|
| UDLL |
FAIL
|
Signalling
| Address |
Set |
Label |
| TN00:0 |
false |
|
| TN00:1 |
false |
|
| TN00:2 |
false |
|
| TN00:3 |
false |
|
| TN00:4 |
false |
|
| TN00:5 |
false |
|
| TN00:6 |
false |
|
| TN00:7 |
false |
|
| TN01:0 |
false |
|
| TN01:1 |
true |
|
| TN01:2 |
false |
|
| TN01:3 |
false |
|
| TN01:4 |
true |
|
| TN01:5 |
true |
|
| TN01:6 |
false |
|
| TN01:7 |
false |
|
| TN02:0 |
true |
|
| TN02:1 |
true |
|
| TN02:2 |
false |
|
| TN02:3 |
false |
|
| TN02:4 |
false |
|
| TN02:5 |
false |
|
| TN02:6 |
false |
|
| TN02:7 |
false |
|
| TN03:0 |
false |
|
| TN03:1 |
false |
|
| TN03:2 |
false |
|
| TN03:3 |
false |
|
| TN03:4 |
true |
|
| TN03:5 |
false |
|
| TN03:6 |
false |
|
| TN03:7 |
true |
|
| TN04:0 |
true |
|
| TN04:1 |
false |
|
| TN04:2 |
true |
|
| TN04:3 |
true |
|
| TN04:4 |
false |
|
| TN04:5 |
false |
|
| TN04:6 |
false |
|
| TN04:7 |
false |
|
| TN05:0 |
true |
|
| TN05:1 |
true |
|
| TN05:2 |
true |
|
| TN05:3 |
false |
|
| TN05:4 |
false |
|
| TN05:5 |
true |
|
| TN05:6 |
true |
|
| TN05:7 |
true |
|
| TN06:0 |
false |
|
| TN06:1 |
false |
|
| TN06:2 |
false |
|
| TN06:3 |
false |
|
| TN06:4 |
false |
|
| TN06:5 |
false |
|
| TN06:6 |
false |
|
| TN06:7 |
false |
|
| TN07:0 |
false |
|
| TN07:1 |
false |
|
| TN07:2 |
false |
|
| TN07:3 |
false |
|
| TN07:4 |
false |
|
| TN07:5 |
false |
|
| TN07:6 |
false |
|
| TN07:7 |
false |
|
| TN08:0 |
false |
|
| TN08:1 |
false |
|
| TN08:2 |
false |
|
| TN08:3 |
false |
|
| TN08:4 |
false |
|
| TN08:5 |
false |
|
| TN08:6 |
false |
|
| TN08:7 |
false |
|
| TN09:0 |
false |
|
| TN09:1 |
false |
|
| TN09:2 |
false |
|
| TN09:3 |
false |
|
| TN09:4 |
false |
|
| TN09:5 |
true |
|
| TN09:6 |
true |
|
| TN09:7 |
false |
|
| TN0A:0 |
false |
|
| TN0A:1 |
false |
|
| TN0A:2 |
false |
|
| TN0A:3 |
false |
|
| TN0A:4 |
false |
|
| TN0A:5 |
true |
|
| TN0A:6 |
false |
|
| TN0A:7 |
false |
|
| TN0B:0 |
false |
|
| TN0B:1 |
false |
|
| TN0B:2 |
false |
|
| TN0B:3 |
false |
|
| TN0B:4 |
false |
|
| TN0B:5 |
false |
|
| TN0B:6 |
false |
|
| TN0B:7 |
false |
|
| TN0C:0 |
false |
|
| TN0C:1 |
false |
|
| TN0C:2 |
false |
|
| TN0C:3 |
false |
|
| TN0C:4 |
false |
|
| TN0C:5 |
false |
|
| TN0C:6 |
false |
|
| TN0C:7 |
false |
|
| TN0D:0 |
true |
|
| TN0D:1 |
false |
|
| TN0D:2 |
false |
|
| TN0D:3 |
true |
|
| TN0D:4 |
false |
|
| TN0D:5 |
false |
|
| TN0D:6 |
false |
|
| TN0D:7 |
false |
|
| TN0E:0 |
false |
|
| TN0E:1 |
false |
|
| TN0E:2 |
false |
|
| TN0E:3 |
false |
|
| TN0E:4 |
false |
|
| TN0E:5 |
false |
|
| TN0E:6 |
false |
|
| TN0E:7 |
false |
|
| TN0F:0 |
false |
|
| TN0F:1 |
false |
|
| TN0F:2 |
false |
|
| TN0F:3 |
false |
|
| TN0F:4 |
false |
|
| TN0F:5 |
false |
|
| TN0F:6 |
false |
|
| TN0F:7 |
false |
|